1. Field of Invention
Embodiments of the present invention described herein generally relate to semiconductor devices such as flash memory devices and methods of fabricating the same.
2. Description of the Related Art
A typical semiconductor device is fabricated by forming device isolation layers to define active regions in predetermined places of a semiconductor substrate and subsequently forming gate electrodes crossing over the active regions. The device isolation layers are generally formed after forming a trench mask pattern using a technique of shallow trench isolation (STI) that anisotropically etches the semiconductor substrate under the trench mask pattern. The gate electrodes are typically formed by depositing a gate insulation film and a gate conductive film in sequence on the active region and patterning the gate conductive film to intersect the active region.
Meanwhile, a nonvolatile memory device such a flash memory device also includes a floating gate electrode placed under the gate electrode. Forming the floating gate electrode is conducted generally using two patterning steps with two mask patterns different from each other (i.e., being arranged in directions parallel and vertical to the active region). In this process for forming the floating gate electrode, a patterning step is performed in the direction vertical to the active region to form the gate electrode. But, in the case of a patterning step in the direction parallel to the active region, an expensive photographic process is additionally needed, and a precise control of photographic processing parameters such as overlay characteristics is needed.
With high integration density of semiconductor devices, it becomes more difficult to regulate the parameters of photographic process. Accordingly, a way of patterning a floating gate conductive film in self-alignment has been proposed for replacing the patterning step based on a photographic process.
FIGS. 1 through 3 are perspective views showing a general method of fabricating a flash memory device.
Referring to FIG. 1, after forming a trench mask pattern 20 on a semiconductor substrate 10, trenches 15 are formed to define active regions by using the trench mask pattern 20 as an etch mask. Here, the trench mask pattern 20 may include lower and upper mask patterns 21 and 22 which are stacked in sequence. The lower and upper mask patterns, 21 and 22, are each used as a gate insulation film and a floating gate electrode in a memory transistor of the flash memory device.
Next, a device isolation pattern 30 is formed to fill the trenches 15. The device isolation pattern 30 is formed by forming a device isolation layer to fill the trenches 15 and etching the device isolation layer to expose the upper sidewalls of the upper mask pattern 22. In this conventional art, the device isolation layer may be a silicon oxide film formed by chemical vapor deposition (CVD). But, as well known, when a gap region (e.g., the trench 15) with a large aspect ratio is filled up with a layer form by CVD, discontinuous interfaces or voids are generated due to the step coverage characteristics of the CVD layer (see “Silicon Processing for the VLSI Era: Volume 1—Process Technology” written by Stanley Wolf, pp. 185 of 1990 edition, Lattice Press, and “Silicon Processing for the VLSI Era: Volume 2—Process Integration” written by Stanley Wolf, pp. 202 of 1990 edition by Lattice Press). As the device isolation pattern 30 is formed by etching the device isolation layer including the discontinuous interfaces or voids, a seam 35 is formed at the upper center of the device isolation pattern 30 as shown in FIG. 1.
Referring to FIG. 2, an intergate insulation film 40 and a control gate film 50 are sequentially deposited on the resultant structure including the device isolation pattern 30. Referring to FIG. 3, the intergate insulation film 40, the control gate film 50, and the upper mask pattern 22 are patterned to form gate lines crossing over the active regions. The gate line is composed of an intergate insulation pattern 45, a control gate electrode 55, and a floating gate electrode 25 interposed between the intergate insulation pattern 45 and the active region, which are sequentially stacked with crossing over the active regions.
As shown in FIG. 3, the intergate insulation film 40 and the control gate film 50 may be formed to fill the seam 35, But, the control gate film 50 formed in the seam 35 may remain therein without being etched away clearly. Such remaining portions of the control gate film 50 in the seam 35 can act as electrical paths 99 causing undesirable bridges between adjacent gate lines and, as a result, yield a defective product.